1. Technical Field
One or more embodiments of the present invention relate to a semiconductor device which is used for adjustment of output of a Hall element or the like.
2. Background Art
Recently, in an image stabilization circuit of an imaging device such as a digital still camera and a digital video camera or in a vibration circuit of a portable phone, a position detecting circuit which uses a Hall element for detecting a position of an optical element such as a lens and a vibrating element is used.
An equivalent circuit of the Hall element is represented as a bridge circuit of resistors R1˜R4. An output signal of the Hall element contains an offset component because of influences of variations of the resistors, according to a combination of a terminal to which a power supply voltage Vcc is applied and a terminal from which the output signal is output.
Because of this, as shown in FIG. 8, an offset cancelling circuit 100 is used which includes a Hall element 10, an amplification circuit 12, and an averaging circuit 14. The offset cancelling circuit 100 is formed as a semiconductor device formed over a semiconductor substrate along with other peripheral circuits. The averaging circuit 14 comprises switching elements S9˜S19, capacitors C1˜C4, an operational amplifier 14a, and a reference voltage generating circuit 14b. The switching elements S9˜S19 connect some of output terminals of operational amplifiers 12a and 12b, terminals of the capacitors C1˜C4, and an input terminal of the operational amplifier 14a to each other.
A switching element S1 is switched ON and a switching element S6 is switched OFF so that the power supply voltage Vcc is applied to a connection point A of the resistors R1 and R2, a switching element S2 is switched ON and a switching element S8 is switched OFF so that a connection point C of the resistors R3 and R4 is grounded, a switching element S7 is switched ON and a switching element S4 is switched OFF so that a connection point D of the resistors R1 and R4 is connected to a non-inverting input terminal (+) of the operational amplifier 12b, and a switching element S5 is switched ON and a switching element S3 is switched OFF so that a connection point B of the resistors R2 and R3 is connected to a non-inverting input terminal (+) of the operational amplifier 12a. In addition, of the switching elements S9˜S19, the switching elements S13 and S14 are switched ON and all other switching elements are switched OFF so that an output of the operational amplifier 12a is connected to a positive terminal of the capacitor C1 and an output of the operational amplifier 12b is connected to a negative terminal of the capacitor C1. Thus, a state is realized in which the capacitor C1 is charged by the output voltages of the operational amplifiers 12a and 12b. 
Then, the switching element S6 is switched ON and the switching element S1 is switched OFF so that the connection point A of the resistors R1 and R2 is connected to the non-inverting input terminal (+) of the operational amplifier 12a, the switching element S8 is switched ON and the switching element S2 is switched OFF so that the connection point C of the resistors R3 and R4 is connected to the non-inverting input terminal (+) of the operational amplifier 12b, the switching element S4 is switched ON and the switching element S7 is switched OFF so that the connection point D of the resistors R1 and R4 is grounded, and the switching element S3 is switched ON and the switching element S5 is switched OFF so that the power supply voltage Vcc is applied to the connection point B of the resistors R2 and R3. In addition, of the switching element S9˜S19, the switching element S15 and S16 are switched ON and all other switching elements are switched OFF so that the output of the operational amplifier 12a is connected to a negative terminal of the capacitor C2 and the output of the operational amplifier 12b is connected to a positive terminal of the capacitor C2. Thus, a state is realized in which the capacitor C2 is charged by the output voltages of the operational amplifiers 12a and 12b. 
In this manner, the circuit is switched between two modes in which voltages are applied to change direction of the current flowing in the Hall element 10, and the capacitors C1 and C2 are charged with Hall voltages V1 and V2 in two directions (90°) for four terminals of the Hall element 10. The charging voltage V1 has a value in which an offset voltage Voff is added to the Hall voltage Vhall in the first mode. That is, the charging voltage V1=Vhall+Voff. When the current flowing to the Hall element 10 is changed by 90°, the offset voltage Voff of the Hall element 10 appears in an opposite direction, and thus the charging voltage V2 has a value in which the offset voltage Voff is subtracted from the Hall voltage Vhall in the second mode. That is, the charging voltage V2=Vhall−Voff.
In an output state, switching elements S13˜S16 are switched OFF, to disconnect the operational amplifiers 12a and 12b and the capacitors C1 and C2. In addition, the switching elements S11, S12, and S19 are switched ON and the switching element S18 is switched OFF so that the positive terminals of the capacitors C1 and C2 are commonly connected to one end of the input terminal of the operational amplifier 14a through a capacitor C4. Moreover, the switching elements S9 and S10 are switched ON so that the negative terminals of the capacitors C1 and C2 are commonly connected to the other end of the input terminal of the operational amplifier 14a. The other end of the operational amplifier 14a is set at Vref generated by a reference voltage generating circuit 14Q. The switching element S17 for deleting charge of a capacitor C3 is also set to the OFF state.
When the circuit is set in such an output state, the capacitors C1 and C2 are connected in parallel, and the charges stored in the capacitors C1 and C2 are re-distributed to the capacitors C1˜C4, so that the charging voltages V1 and V2 are averaged. With this process, the offset value Voff of the output voltage of the Hall element 10 is cancelled, and the output voltage Vout is output.
As shown in FIG. 9, the Hall element 10 is formed as a bridge circuit of resistors R1˜R4 over a semiconductor substrate. In the Hall element 10, a line L1 extends from the connection point A of the resistors R1 and R2 along the resistor R2 in a direction toward a position where the resistor R3 is placed. A line L2 extends from the connection point D of the resistors R1 and R4 along the resistor R4 in a direction toward a position where the resistor R3 is placed. A line L3 extends from the connection point B of the resistors R2 and R3 in a direction away from the resistor R3. A line L4 extends from the connection point C of the resistors R3 and R4 in a direction away from the resistor R3. In the Hall element 10 having such a layout of lines, the application state of voltages is switched using the lines L1˜L4 when the capacitor C1 is charged or when the capacitor C2 is charged.
In the offset cancelling circuit 100 of the related art, a configuration is employed in which the circuit is switched between the first mode as shown in FIG. 10 in which the power supply voltage Vcc is applied from the line L1, the line L4 is grounded, and the outputs of the Hall element 10 are obtained from the lines L2 and L3 and the second mode as shown in FIG. 11 in which the power supply voltage Vcc is applied from the line L3, the line L2 is grounded, and the outputs of the Hall element 10 are obtained from the lines L1 and L4.
The resistors R1˜R4 of the Hall element 10 are influenced by the voltages applied to nearby lines L1˜L4, and the respective resistance values vary. In particular, in the offset cancelling circuit 100, the resistor R2 formed along the line L1 tends to be influenced by the voltage applied to the line L1, and the resistor R4 formed along the line L2 tends to be influenced by the voltage applied to the line L2. In other words, while in the first mode, the resistor R2 is influenced by the power supply voltage Vcc and the resistor R4 is influenced by the output voltage of the Hall element 10, in the second mode, the resistor R2 is influenced by the output voltage of the Hall element 10 and the resistor R4 is influenced by the ground voltage.
As described, in the offset cancelling circuit 100, the influences of the lines L1˜L4 on the resistors R1˜R4 are not symmetric in the first mode and the second mode. Additionally, the offset due to the influences of lines L1˜L4 is superposed on the output from the Hall element 10, which cannot be cancelled by the offset cancelling circuit 100.